Method and system for use of a field programmable gate array (FPGA) function within an application specific integrated circuit (ASIC) to enable creation of a debugger client within the ASIC

ABSTRACT

An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions and at least one bus coupled to at least a portion of the logic functions. The standard cell also includes a plurality of internal signals from the plurality of logic functions and a field programmable gate array (FPGA) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FPGA function includes a debug client function that observes and manipulates the at least one bus and the plurality of internal signals. A system and method in accordance with the present invention utilizes a debug function within a standard cell design to create an internal-to-the-ASIC debugging (software, hardware or both) function. The system and method is provided by connection of internal buses and signals of interest to a debug client function within the FPGA function. The debug client function observes and, if needed, manipulates internal buses and signals and communicates with an external to the ASIC debugging system.

CROSS-RELATED APPLICATIONS

[0001] The present application is related to the following listed sevenapplications: Ser. No. ______ (RPS920010125US1) entitled “FieldProgrammable Network Processor and Method for Customizing a NetworkProcessor;” Ser. No. ______ (RPS920010126US1), entitled “Method andSystem for Use of an Embedded Field Programmable Gate Array Interconnectfor Flexible I/O Connectivity;” Ser. No. ______ (RPS 920010128US1),entitled “Method and System for Use of a Field Programmable FunctionWithin an Application Specific Integrated Circuit (ASIC) To AccessInternal Signals for External Observation and Control;” Ser. No. ______(RPS920010129US1), entitled “Method and System for Use of a FieldProgrammable Interconnect Within an ASIC for Configuring the ASIC;” Ser.No. ______ (RPS920010130US1), entitled “Method and System for Use of aField Programmable Function Within a Chip to Enable Configurable I/OSignal Timing Characteristics;” Ser. No. ______ (RPS920010131US1),entitled “Method and System for Use of a Field Programmable FunctionWithin a Standard Cell Chip for Repair of Logic Circuits;” and Ser. No.______ (RPS920010132US1), entitled “Method and System for Use of a FieldProgrammable Gate Array 9FPGA) Cell for Controlling Access to On-ChipFunctions of a System on a Chip (S)C) Integrated Circuit;” assigned tothe assignee of the present application, and filed on the same date.

FIELD OF THE INVENTION

[0002] The present invention relates generally to an applicationspecific integrated circuit (ASIC) and specifically to providing an FPGAfunction to allow for the use of a debug client within the ASIC.

BACKGROUND OF THE INVENTION

[0003] In today's (logical) ASIC test environment, application specificintegrated circuits (ASICs) are extremely dense with various functionswhile having limited I/O with respect to those functions. Often, thereare significant, complex functions connection with only internal ASICbuses and signal paths, which are not exposed via an I/O pin. Further,due to the density and complexity of functions, it would not bepractical to bring out all needed debug functions, as this would resultin potentially thousands of I/O pins.

[0004] Historically, functional entities were embodied in multiple ASICswith an exposed bus and signal paths between the ASICs (functions). Thisenabled the use of logical analyzers, logic debuggers and like tools tobe used to debug the system. This is not possible with today's ASICs asthere is no physical method available to place the debuggers on aninternal-to-the-ASIC bus and no method to disconnect and tie up or downinternal-to-the-ASIC signal paths.

[0005] Accordingly, what is needed is a system and method for allowingthe debugging of an ASIC via access to the ASIC's internal signals. Thepresent invention addresses such a need.

SUMMARY OF THE INVENTION

[0006] An application specific integrated circuit (ASIC) is disclosed.The ASIC includes a standard cell. The standard cell includes aplurality of logic functions and at least one bus coupled to at least aportion of the logic functions. The standard cell also includes aplurality of internal signals from the plurality of logic functions anda field programmable gate array (FPGA) function coupled to the at leastone bus and the plurality of internal signals. The FPGA functionincludes a debug client function that observes and manipulates the atleast one bus and the plurality of internal signals.

[0007] A system and method in accordance with the present inventionutilizes a debug function within a standard cell design to create aninternal-to-the-ASIC debugging (software, hardware or both) function.The system and method is provided by connection of internal buses andsignals of interest to a debug client function within the FPGA function.The debug client function observes and, if needed, manipulates internalbuses and signals and communicates with an external to the ASICdebugging system.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 illustrates the placement of an FPGA function into arepresentative standard cell design.

[0009]FIG. 2 illustrates a logical view of the internals of the debugclient function in accordance with the present invention.

[0010]FIG. 3 illustrates a debug system in accordance with the presentinvention.

DETAILED DESCRIPTION

[0011] The present invention relates generally to an applicationspecific integrated circuit (ASIC) and specifically to providing an FPGAfunction to allow for the debug via the ASIC. The following descriptionis presented to enable one of ordinary skill in the art to make and usethe invention and is provided in the context of a patent application andits requirements. Various modifications to the preferred embodiment andthe generic principles and features described herein will be readilyapparent to those skilled in the art. Thus, the present invention is notintended to be limited to the embodiment shown but is to be accorded thewidest scope consistent with the principles and features describedherein.

[0012]FIG. 1 illustrates the placement of an FPGA function into arepresentative standard cell design 100. In this embodiment, thestandard cell design includes a media access controller (MAC) 102, a PCIbus interface 104, arithmetic logic unit (ALU) 108, a memory 110, a busarbiter 116, a random number generator 114, and encryption key generator112. A plurality of external I/Os 106 are provided to the MAC 102, thePCI bus interface 104 and to the FPGA function 118. In addition, thereis an internal bus 121 between the generator 114 and the generator 112.An FPGA debug client 120 is within the FPGA function 118. Althoughspecific functions and buses are illustrated in the standard cell, oneof ordinary skill in the art recognizes that a variety of functionscould be utilized and that use would be within the spirit and scope ofthe present invention.

[0013] As is seen, all internal buses and signals of interest are“bused” or connected to the FPGA function 118. In the preferredembodiment, the FPGA function 118 itself has external I/O connectivity.An alternative embodiment would be to reuse an existing I/O structure,such as a PCI bus, but this has inherent disadvantages when trying todebug a function that also uses that I/O structure. As has beendescribed above, the FPGA function 118 includes a debug client function120 thereafter. The debug client function 120 can be utilizedadvantageously to observe and manipulate the buses and internal signalsof the standard cell. For a further description of the features of thedebug client function 120, refer now to the following description inconjunction with the accompanying figures.

[0014]FIG. 2 illustrates a logical view of the internals of the debugclient function 120 in accordance with the present invention. It is notmeant to illustrate how one would physically program this area. Thedebug client function 120 includes the external communicator logic 122,which communicates with interface logic 123. This interface logic 123includes signal and bus state storage logic 124, stateful and statelesscomparators and client control logic 126 and signal and bus output logic128. The logic 126 communicates with the logic 124 and logic 128. Asignal and bus selector logic 130 communicates with the interface logic123 and with the internal signals and bus. The function and features ofeach of the logic elements of the debug client function 120 aredescribed below.

[0015] Signal and Bus Selector Logic Function Block 130

[0016] The signal and bus selector logic function block 130 can beembodied either as physical bus selectors gates using standard busselector techniques in which all signals are sent through this selectorlogic and the FPGA logic then selects the ones of interest or as virtualselection (all signals of interest are available at a particular inputpoint, tied up or down as appropriate, but only those points of interestare connected to and enabled when the FPGA is programmed—de factoselection).

[0017] Interface Logic 123

[0018] Signal and Bus State Storage Logic Function Block 124

[0019] The signal and bus state storage logic function block 124 storesthe state of the signals of interest (“of interest” is defined through adebugger server) for later retrieval by a debugger server.

[0020] Stateful and Stateless Comparators and Client Control LogicFunction Block 126

[0021] The stateful and stateless comparators and client control logicfunction block 126 is the logic that compares the signals of interestwith the “trigger” pattern that is down-loaded from the debugger serverand upon a match, directs the signal and bus state storage logicfunction block 124 to store the signals of interest.

[0022] Signal and Bus Output Logic Function Block 128

[0023] The signal and bus output logic function block 128 is logic thatthe debugger server uses to manipulate the internal signals on the ASIC.This may include clock signals, for single step debugging and may be theresult of a logical expression derived from the control logic, i.e.,when the write strobe on the internal RAM goes active and the RAMaddress bus has address “ABCDEF42”, then halt an internal ASIC clock.

[0024] External Communication Logic Function Block 122

[0025] The external communication logic function block 122 provides theexternal I/O function for the debug client to communicate with the debugserver.

[0026] Debug System

[0027]FIG. 3 illustrates a debug system 240 in accordance with thepresent invention. Note that the preferred embodiment of the debuggerserver 200 is a general purpose processing system running a debuggerapplication (a PC). The communications link between the systems does nothave to be as rapid as the internal ASIC communications links because ofthe debug client.

[0028] The debug client function 120 contains either an independent ordependent debugger client. The preferred embodiment is a simpledependent client, with each debugging session information downloaded(the FPGA is “programmed”) by the debugger server 240, much like themodel of physically connected leads from external buses to a logicanalyzer, then setting a trigger point and observing the system. Upontrigger, the system server 240 will capture selected information. Thissame concept is embodied in the independent debugger client with theaddition that one may wish to set a bus or signal to a know value,either before the observation period or as a result of an observedaction. This same process could be used to hold part or all of an ASIC'sclocks in a known state or to hold part or all of an ASIC's functionalareas in reset modes.

[0029] Note that as described, this system could be used to debughardware values (e.g., the value of signals within a hardware functionblock). However, a significant extension can be made by altering the waythat the debugger server 240 uses the debug client function, which willenable this same concept to be used to debug software. If instead oftriggering based on hardware values, the triggers are based on softwarevalues (assuming the debug client function's ability to manage theinstruction pointer logic within the ASIC and to observer and manipulateregisters and memory) then one can create a debugging system forsoftware. Given the complexities of software systems today and the oftenwholly within the ASIC software interfaces, this could be of more valuethan hardware debugging.

[0030] A first distinguishing feature between a system and method inaccordance with the present invention and achieving a similar functionwithin the hard-coded portion of a standard ASIC is that this methodallows the user to change the software or hardware debug client afterthe ASIC has been cast into silicon. In addition, the differentproducers of the ASIC debugger system can place their own unique valueadded client in the ASIC, thus with one ASIC, enabling the creation ofmultiple debuggers from multiple different companies.

[0031] A second distinguishing feature between a system and method inaccordance with the present invention and achieving a similar functionwithin the hard-coded portion of a standard ASIC is that this methodallows the user to change the debug process after the ASIC has been castinto silicon. It is not possible to know all possible debugconsiderations when the ASIC is created. As the complexity of the ASICsincrease and the programmability (more software bugs that must be found)of the ASICs increase, the ability to change the debug process willbecome increasingly important.

[0032] An additional advantage is that this process allows theindependent development of the software debugging system with respect tothe ASIC development. This would allow an ASIC vendor to define the FPGAcharacteristics and the available internal signals to a third partydebugger developer, thus:

[0033] 1. allowing parallel development of the ASIC and the debuggingtools

[0034] 2. allowing the debugging tools to be developed by a third party,saving the ASIC vendor the resource expenditure.

[0035] Another advantage is that the same ASIC can simultaneouslysupport multiple debugging systems by different companies. For example,if two manufacturers both wanted to build a FPGA embodied debuggerclient that worked with their proprietary system, they could both dothat with the same ASIC.

[0036] A system and method in accordance with the present inventionutilizes a debug function within a standard cell design to create aninternal-to-the-ASIC debugging (software, hardware or both) function.The system and method is provided by connection of internal buses andsignals of interest to a debug client function within the FPGA function.The debug client function observes and, if needed, manipulates internalbuses and signals and communicates with an external to the ASICdebugging system.

[0037] Although the present invention has been described in accordancewith the embodiments shown, one of ordinary skill in the art willreadily recognize that there could be variations to the embodiments andthose variations would be within the spirit and scope of the presentinvention. Accordingly, many modifications may be made by one ofordinary skill in the art without departing from the spirit and scope ofthe appended claims.

What is claimed is:
 1. An application specific integrated circuit (ASIC)comprising: a standard cell, the standard cell including a plurality oflogic functions; at least one bus coupled to at least a portion of thelogic functions; a plurality of internal signals from the plurality oflogic functions; and a field programmable gate array (FPGA) functioncoupled to the at least one bus and the plurality of internal signals,the FPGA function including a debug client function that observes andmanipulates the at least one bus and the plurality of internal signals.2. The ASIC of claim 1 wherein the at least one bus comprises aninternal bus.
 3. The ASIC of claim 2 wherein the debug client functionobserves and manipulates at least one point of interest on the standardcell.
 4. The ASIC of claim 1 wherein the debug client function isprogrammed by a server.
 5. The ASIC of claim 1 wherein the debug clientfunction further includes: an external communicator logic function forreceiving and transmitting information to a server; selector logiccoupled to the at least one bus and the plurality of internal signals,and an interface logic coupled between the external communicator logicand the selector logic for providing communication therebetween.
 6. TheASIC of claim 5 wherein the interface logic comprises: a storage logicfunction for storing a state of signals of interest from the selectorlogic and providing the state to a server; a comparator logic functioncoupled to the storage logic function for comparing the signals ofinterest from the selector block function; and an output logic functioncoupled to the comparator logic function for controlling the internalsignals on the ASIC.
 7. The ASIC of claim 4 wherein the server utilizesthe debug client to debug hardware within at least one of the pluralityof logic functions.
 8. The ASIC of claim 4 wherein the server utilizesthe debug client to debug software within at least one of the pluralityof logic functions.
 9. A debug client function within an applicationspecific integrated circuit (ASIC), the debug client function beingwithin a field programmable gate array (FPGA) function; the client debugfunction comprising: an external communicator logic function forreceiving and transmitting information concerning a plurality of signalsof the ASIC to a server; selector logic coupled to the at least one busof the ASIC and the plurality of internal signals, and an interfacelogic coupled between the external communicator logic and the selectorlogic for providing communication therebetween.
 10. The ASIC of claim 9wherein the at least one bus comprises an internal bus.
 11. The ASIC ofclaim 9 wherein the debug client function observes and manipulates atleast one point of interest on the standard cell.
 12. The ASIC of claim9 wherein the debug client function is programmed by a server.
 13. TheASIC of claim 9 wherein the interface logic comprises: a storage logicfunction for storing a state of signals of interest from the selectorlogic and providing the state to a server; a comparator logic functioncoupled to the storage logic function for comparing the signals ofinterest from the selector block function; and an output logic functioncoupled to the comparator logic function for controlling the internalsignals on the ASIC.
 14. The ASIC of claim 12 wherein the serverutilizes the debug client to debug hardware within at least one of theplurality of logic functions.
 15. The ASIC of claim 12 wherein theserver utilizes the debug client to debug software within at least oneof the plurality of logic functions.